Semiconductor device with compensated threshold voltage and method for making same

ABSTRACT

A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity type. At least one second pocket may be formed adjacent to each of the junctions and stacked against each of the first pockets. The second pocket may be doped with a dopant of a second conductivity type such that the dopant concentration in the second pocket is less than the dopant concentration in the first pockets. The second pocket may reduce a local substrate concentration without changing the conductivity type of the channel region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to a semiconductor device, suchas an MOS transistor, in which there is compensation for the drop in thethreshold voltage (V_(th)) due to the short-channel effects, and to aprocess for fabrication of such a semiconductor device.

2. Description of the Related Art

For a given nominal channel length (L) of a transistor, the thresholdvoltage (V_(th)) drops suddenly, in particular for short-channeltransistors (i.e., those having a channel length of less than 0.25 μmand typically a channel length, L, of about 0.18 μm).

The threshold voltage of a semiconductor device such as an MOStransistor, in particular a short-channel device, is a criticalparameter of the device. This is because the leakage current of thedevice (for example, of the transistor) depends strongly on thethreshold voltage. Taking into consideration current supply voltages andthose envisaged in the future (from 0.9 to 1.8 volts) for such devicesand the permitted leakage currents (I_(off) of approximately 1 nA/μm),the threshold voltage V_(th) must have values of approximately 0.2 to0.25 volts.

The sudden voltage drop (or roll-off) in the zones of the channel regionof the semiconductor device results in dispersion of the electricalcharacteristics of the device and makes it difficult to obtain thedesired threshold voltages.

To remedy this threshold voltage roll-off in semiconductor devices suchas MOS transistors, it has been proposed, as described in the article“Self-Aligned Control of Threshold Voltages in Sub-0.02-μm MOSFETs” byHajima Kurata and Toshihiro Sugii, IEEE Transactions on ElectronDevices, Vol. 45, No. Oct. 10, 1998, to form, in the channel region,pockets adjacent to the source and drain region junctions that have aconductivity of the same type as the substrate; but in which, the dopantconcentration is greater than that of the substrate.

Although this solution reduces the threshold voltage roll-off gradientin the channel region, the short-channel effects lead to a more rapidroll-off of the threshold voltage, V_(th), than the increase in thethreshold voltage that can be obtained by incorporating the compensationpockets of the prior art.

Consequently, although these compensation pockets allow partial localcompensation for the roll-off of the threshold voltage, V_(th), it isnot possible to obtain complete compensation for the roll-off over theentire channel region range desired.

Therefore a semiconductor device, such as an MOS transistor, thatremedies the drawbacks of the devices of the prior art may be desired.

More particularly, a semiconductor device, such as an MOS transistor,whose voltage threshold roll-off due to the short-channel effects isalmost fully compensated for may be desired. This makes it possible toachieve channel lengths which are arbitrarily small but non-zero.

Also a semiconductor device, such as an MOS transistor, may have aconstant threshold voltage, V_(th), when the channel length, L,decreases down to very small effective channel lengths, for example,0.025 μm or less.

A process for fabricating a semiconductor device may apply to deviceshaving channels of arbitrarily small length, these being, moreover,technologically realizable.

DESCRIPTION OF THE INVENTION

A semiconductor device is described that may have a semiconductorsubstrate with a predetermined concentration, Ns, of a dopant of a firstconductivity type. The device may have source and drain regions whichare doped with a dopant of a second conductivity type, which is oppositeof the first conductivity type. Junctions delimiting a channel region ofpredetermined nominal length, L_(N), may be defined in the substrate. Afirst pocket adjacent to each of the junctions and having apredetermined length, Lp, may be defined. The first pockets may be dopedwith a dopant of the first conductivity type but with a localconcentration, Np, which locally increases the net concentration in thesubstrate. The device may include at least one second pocket locatedadjacent to each of the junctions and stacked against each of the firstpockets. These second pockets may have a length, Ln, such that Ln>Lp.The second pockets may be doped with a dopant of the second conductivitytype and have a concentration, Nn, such that Nn<Np. This may locallydecrease the net concentration of the substrate without changing theconductivity type.

In an embodiment, the second pockets include a plurality of elementarypockets stacked against one another. Each elementary pocket of a givenrank, i, may have a predetermined length, Ln_(i), and a predeterminedconcentration, Nn_(i), of a dopant of the second conductivity typesatisfying the following relationships:

Ln₁>Lp,

Ln_(i−1)<Ln_(i)<Ln_(i+1),

Nn_(i−1)>Nn_(i)>Nn_(i+1), and

the sum, ΣNn_(i), of the concentrations of the dopant of the secondconductivity type in the elementary pockets may be such that:

ΣNn_(i)<Ns.

In other words, the second pockets decrease the net concentration ofdopant of the first conductivity type both in the first pockets and inthe channel region. However, they do not change the conductivity type ofthe first pockets nor of the channel region.

A process for fabricating a semiconductor device as defined above isdescribed. The process may include the formation of a source region andof a drain region in a semiconductor substrate having a predeterminedconcentration, Ns, of a dopant of a first conductivity type. The sourceregion and the drain region may be doped with a dopant of a secondconductivity type, which is opposite of the first conductivity type. Thesource and drain regions may form one or more junctions in the substratesuch that the junctions delimit between them a channel region. Thechannel region may have a predetermined nominal length, L_(N). In thechannel region in a zone adjacent to each of the junctions, one or morefirst pockets may be formed having a predetermined length, Lp, and apredetermined concentration, Np. This may locally increase the netconcentration in the substrate above Ns. The process may furthermoreinclude the implantation, in the channel region, of a dopant of thesecond conductivity type, which is opposite of the first conductivitytype. This may be done under a set of conditions such that at least onesecond pocket is formed in the channel region. Each second pocket may bestacked against each of the first pockets, respectively. The secondpocket may have a length, Ln, such that Ln>Lp, and a concentration, Nn,of a dopant of the first type such that Nn<Np. This may locally decreasethe net concentration in the substrate, without changing theconductivity type.

In a preferred embodiment, the implantation of the dopant of the secondconductivity type consists of a series of successive implantations undera set of conditions such that the second pockets formed each consist ofa plurality of elementary pockets stacked against one another. Eachelementary pocket of a given rank, i, may have a length, Ln_(i), and aconcentration, Nn_(i), of a dopant of the second conductivity typesatisfying the relationships:

Ln₁>Lp,

Ln_(i−1)<Ln_(i)<Ln_(i+1),

Nn_(i−1)>Nn_(i)>Nn_(i+1), and

the sun, ΣNn_(i), of the concentrations of the dopant of the secondconductivity type in the elementary pockets being such that:

ΣNn_(i)<Ns.

The lengths Lp and Ln of the pockets are taken from the junctions.

Implantation of a dopant in a semiconductor substrate is a known processand it is possible, in the present process, to use any implantationprocess conventionally used in the technology of semiconductors.

As is known, the formation of doped pockets in a semiconductor substratedepends on the angle of incidence of the implantation with respect tothe normal to the substrate, on the implantation dose, and on theimplantation energy of the dopant. Thus, by varying the angle ofincidence and the dopant dose, it is possible to increase the length ofthe implanted pocket and to vary the dopant concentration.

As a variant, in order to vary the length of the second implantedpockets and their dopant concentration, successive implantation stepsmay be carried out with the same angle of incidence with respect to thenormal, the same dose, and the same implantation energy. However,subjecting the device to a different annealing heat treatment step aftereach successive implantation step may make the dopant implanted in thesubstrate diffuse differently for each implanted pocket.

BRIEF DESCRIPTION OF THE DRAWINGS

The remainder of the description refers to the appended figures, whichshow respectively:

FIG. 1, a first embodiment of a semiconductor device, such as an MOStransistor;

FIG. 2, a second embodiment of a semiconductor device; and

FIG. 3, a graph of the threshold voltage (V_(th)) for varioussemiconductor devices as a function of the effective channel length.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a first embodiment of a semiconductor device, such as anMOS transistor. The semiconductor device may include a semiconductorsubstrate 1, which may be, for example, a silicon substrate doped with adopant of a first conductivity type (for example, p-type conductivity).Source 2 and drain 3 regions may be formed in the substrate 1 and dopedwith a dopant of a second conductivity type, which is opposite of thefirst conductivity type (for example, an n-type dopant). The source anddrain regions may, in the substrate, define junctions 4, 5 delimitingbetween them a channel region 6.

The channel region 6 may be covered with a gate oxide layer 11 (forexample, a thin silicon oxide layer), which is itself surmounted by agate 12 (for example, a gate made of silicon). The gate 12 may beflanked on two opposed sides by spacers 13, 14 made of a suitabledielectric.

To reduce the rate of roll-off of the threshold voltage, V_(th), in thechannel region 6, two first pockets 7, 8 are formed in the channelregion. Each pocket may be adjacent to one of the junctions 4, 5,respectively. These pockets are doped by means of a dopant of the firstconductivity type, p, but with a concentration, Np, of dopant whichlocally increases the concentration in the substrate to above Ns and hasa length, Lp, as short as possible.

Two second pockets 9, 10 are formed in the channel region 6. The secondpockets are each stacked against one of the first pockets, but with alength, Ln, greater than the length, Lp, o f the first pockets. Thesecond pockets are doped with a dopant of the second conductivity type.For example, the dopant may be an n-type dopant with a concentration,Nn, such that Nn is less than the concentration Np of dopant of thefirst conductivity type in the substrate.

Thus, in the zones of the second pockets , the net concentration ofdopant of the first conductivity type (for example, the p-type dopant)is decreased but the nature of the conductivity in the channel region isnot changed. The channel may still remain a region of p-typeconductivity.

FIG. 2, in which the same reference numbers denote the same elements aspreviously, shows another embodiment of a semiconductor device. FIG. 2shows that the second pockets 9, 10 may include pluralities ofelementary pockets stacked against one another. For example, pluralitiesof elementary pockets may include three elementary pockets as shown inthe embodiment in FIG. 2.

Each elementary pocket of a given rank, i, has a length, Ln_(i), and aconcentration, Nni, of dopant of the second conductivity type whichsatisfy the following relationships:

Lp<Ln_(i),

Ln_(i−1)<Ln_(i)<Ln_(i+1),

Nn_(i−1)<Nn_(i)<Nn_(i+1), and

the sum ΣNn_(i) of the concentrations of dopant of the secondconductivity type in the elementary pockets being such that:

ΣNn_(i)<Ns.

In other words, the elementary pockets stacked against the first pockets7 and 8 are also stacked against one another. However, they haveincreasing lengths and, concurrently, concentrations of dopant of thefirst conductivity type which decrease as their lengths increase.

Moreover, the sum of the concentrations, ΣNn_(i), of the stackedelementary pockets is such that it remains less than the concentration,Ns, of dopant of the first conductivity type in the substrate so thatthe conductivity type of the channel region 6 is not modified.

Thus, in the case shown in FIG. 2, in which the second pockets consistof three elementary pockets. The lengths and dopant concentrations ofthe elementary pockets satisfy the relationships:

Lp<Ln₁,

Ln₁<Ln₂<Ln₃,

Nn₁>Nn₂>Nn₃, and

Nn₁+Nn₂+Nn₃<Ns.

FIG. 3 shows simulated graphs of the threshold voltage, V_(th), fortransistors having a gate oxide layer 4 nm in thickness and for adrain/source voltage of 1.5 volts as a function of the effective channellength. The lengths, Lp, and the concentrations, Np, of the firstpockets doped with a dopant of the same type as the substrate correspondto the minimum channel length to be obtained and the highest doping.

Curve A corresponds to the stacking of a single second pocket and showsthat a flat V_(th) is obtained for a channel length down to 0.15 μm.

Curve B corresponds to the stacking of two second pockets and shows thata flat V_(th) is obtained for a channel length down to 0.07 μm.

Finally, curve C corresponds to the stacking of seven second pockets andshows that a flat V_(th) can be obtained for a channel length down to0.025 μm.

Thus, the above curves show that the necessary doping levels remainreasonable and make it possible to obtain flat curves of V_(th) as afunction of the effective channel length down to effective lengths of 25nm. This may be so even with gate oxide thicknesses of 4 nm.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate having a predetermined concentration, Ns, of adopant of a first conductivity type; a source region and a drain regiondoped with a dopant of a second conductivity type; junctions, whereinthe junctions delimit a channel region of a predetermined length, L_(N),in the substrate, wherein the junctions are defined by the source regionand the drain region; first pockets located adjacent to each of thejunctions, wherein the pockets have a predetermined length, Lp, whereinthe first pockets are doped with a dopant of the first conductivity typewith a dopant concentration, Np, which locally increases a netconcentration in the substrate above Ns; second pockets located adjacentto each of the junctions and stacked against each of the first pockets,wherein the second pockets have a length, Ln, such that Ln is greaterthan Lp, and wherein the second pockets are doped with a dopant of thesecond conductivity type with a dopant concentration, Nn, such that Nnis less than Np, which locally decreases a net concentration withoutchanging a conductivity type, and wherein Nn is less than Ns; andwherein an overall length of the first pockets and the second pockets isless than the length, L_(N), of the channel region.
 2. The semiconductordevice of claim 1, wherein the second pockets comprise a plurality ofelementary pockets stacked against each other.
 3. The semiconductordevice of claim 1, wherein the second pockets comprise a plurality ofelementary pockets stacked against each other, wherein each elementarypocket comprises a rank, i, and a predetermined length, Ln_(i), whereina predetermined concentration, Nn_(i), of a dopant of the secondconductivity type satisfies the relationships: Ln₁>Lp;Ln_(i−1)<Ln_(i)<Ln_(i+1); Nn_(i−1)>Nn_(i)>Nn_(i+1); and wherein the sum,ΣNn_(i), of the concentrations of the dopant in the elementary pocketssatisfies the relationship, ΣNn_(i)<Ns.
 4. The semiconductor device ofclaim 1, wherein the second pockets comprise a plurality of elementarypockets stacked against each other, and wherein the plurality ofelementary pockets comprises three elementary pockets.
 5. Thesemiconductor device of claim 1, wherein the semiconductor devicecomprises an MOS transistor.
 6. The semiconductor device of claim 1,wherein the first conductivity type comprises p-type conductivity. 7.The semiconductor device of claim 1, wherein the second conductivitytype comprises n-type conductivity.
 8. A method for fabricating asemiconductor device, comprising: forming a semiconductor substrate witha predetermined concentration, Ns, of a dopant of a first conductivitytype; forming a source region and a drain region by doping the sourceand drain regions with a dopant of a second conductivity type, whereinthe second conductivity type is opposite the first conductivity type,wherein the source and drain regions form junctions that delimit achannel region between them, and wherein the channel region comprises apredetermined length, L_(N); forming first pockets adjacent to each ofthe junctions in the channel region, wherein the first pockets areformed by doping each of the first pockets with a predeterminedconcentration, Np, of a dopant of the first conductivity type, whichlocally increases a net concentration in the substrate above Ns, andwherein each of the first pockets comprises a predetermined length, Lp;and implanting in the channel region a dopant of the second conductivitytype under a set of conditions such that second pockets are formed inthe channel region, wherein the second pockets are stacked against eachof the first pockets, wherein the second pockets have a length, Ln, suchthat Ln is greater than Lp, wherein the second pockets have aconcentration, Nn, of the dopant of the second conductivity type suchthat Nn is less than Np, which locally decreases a net concentrationwithout changing a conductivity type, wherein Nn is less than Ns, andwherein the overall length of the first pockets and the second pocketsis less than the nominal length, L_(N), of the channel region.
 9. Themethod of claim 8, wherein implanting in the channel region comprises aseries of successive implanting steps such that the second pocketscomprise a plurality of elementary pockets.
 10. The method of claim 8,wherein implanting in the channel region comprises a series ofsuccessive implantion steps such that the second pockets comprise aplurality of elementary pockets, wherein each elementary pocketcomprises a rank, i, and a predetermined length, Ln_(i), and wherein apredetermined concentration, Nn_(i), of a dopant of the secondconductivity type satisfies the relationships: Ln₁>Lp;Ln_(i−1)<Ln_(i)<Ln_(i+1); Nn_(i−1)>Nn_(i)>Nn_(i+1); and wherein the sum,ΣNn_(i) of the concentrations of the dopant in the elementary pocketssatisfies the relationship, ΣNn_(i)<Ns.
 11. The method of claim 10,further comprising increasing an implantation angle of incidence withrespect to the normal angle to the substrate with each successiveimplantion step and decreasing an implantation dose with each successiveimplantion step.
 12. The method of claim 10, wherein the successiveimplanting steps comprise implanting the dopant of the secondconductivity type using a same angle of incidence with respect to thenormal angle to the substrate, a same implantation dose, and a sameimplantation energy in each successive implantion step, the methodfurther comprising annealing the device in an annealing step after eachsuccessive implantion step, wherein each annealing step is different.13. The method of claim 8, wherein the set of conditions comprises animplantation angle of incidence with respect to the normal angle to thesubstrate, an implantation dose, and an implantation energy.
 14. Themethod of claim 8, wherein the set of conditions comprises animplantation angle of incidence with respect to the normal angle to thesubstrate.
 15. The method of claim 8, wherein the set of conditionscomprises an implantation dose.
 16. The method of claim 8, wherein theset of conditions comprises an implantation energy.
 17. The method ofclaim 8, further comprising forming an MOS transistor with thesemiconductor device.
 18. The method of claim 8, wherein the firstconductivity type comprises p-type conductivity.
 19. The method of claim8, wherein the second conductivity type comprises n-type conductivity.20. A semiconductor device, comprising: a semiconductor substrate havinga concentration, Ns, of a dopant of a first conductivity type; a sourceregion and a drain region doped with a dopant of a second conductivitytype; junctions that define a channel region of a length, L_(N), in thesubstrate, wherein the junctions are defined by the source region andthe drain region; first pockets located adjacent to each of thejunctions, wherein the first pockets have a length, Lp, and wherein thefirst pockets are doped with a dopant of the first conductivity typewith a dopant concentration, Np; second pockets stacked against each ofthe first pockets, wherein the second pockets have a length, Ln, suchthat Ln is greater than Lp, wherein the second pockets are doped with adopant of the second conductivity type with a dopant concentration, Nn,such that Nn is less than Np; and wherein an overall length of the firstpockets and the second pockets is less than the length, L_(N), of thechannel region.